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Chapter 3: Design Rules and Procedures
Fixed-Point Notation
Table 3–1. Fixed-Point Notation
3–3
Description
Notation
Simulink-to-HDL Translation
(1) , (2)
Single bit integer
(BIT)
[1] where:
the single bit can have values 1 or 0
A Simulink single bit integer signal maps to
STD_LOGIC
Notes to Table 3–1 :
(1) STD_LOGIC_VECTOR and STD_LOGIC are VHDL signal types defined in the ( ieee . std_logic_1164.all and ieee.std_logic_signed.all IEEE
library packages).
(2) For designs in which unsigned integer signals are used in Simulink, DSP Builder translates the Simulink unsigned bus type with width w into a
VHDL signed bus of width w + 1 where the MSB bit is set to 0.
Figure 3–1 graphically compares the signed binary fractional, signed binary, and
unsigned binary number formats.
Figure 3–1. Number Format Comparison
Binary Point Location in Signed Binary Fractional Format
For hardware implementation, you must cast Simulink signals into the desired
hardware bus format. Therefore, convert floating-point values to fixed-point values.
This conversion is a critical step for hardware implementation because the number of
bits required to represent a fixed-point value plus the location of the binary point
affects both the hardware resources and the system accuracy.
Choosing a large number of bits gives excellent accuracy—the fixed-point result is
almost identical to the floating-point result—but consumes a large amount of
hardware. You must design for the optimum size and accuracy trade-off. DSP Builder
speeds up your design cycle by enabling simulation with fixed-point and
floating-point signals in the same environment.
The Input block casts floating-point Simulink signals of type double into fixed-point
signals. DSP Builder represents the fixed-point signals in the following signed binary
fractional (SBF) format:
■
[ number of bits ].[]—represents the number of bits to the left of the binary point
including the sign bit.
November 2013
Altera Corporation
DSP Builder Handbook
Volume 2: DSP Builder Standard Blockset
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